This is an implementation for sample hold circuit function that using op amp LM324. This is the figure of the circuit.
In this circuit, the input-to-output wiring has similar to standard configuration, but its operating principle is different. Key advantages include simplicity, no hold step, essentially zero gain error and operation from a single 5V supply. The sample-hold command pulse is applied to Q3, which turns on, causing current source transistor Q4's collector to go to ground potential. Amplifier A1 follows Q4's collector voltage and provides the circuit's output. When the sample-hold command pulse falls, Q4's collector drives a constant current into the 0.01 mF capacitor.
When the capacitor ramp voltage equals the circuit's input voltage, comparator C1 switches, causing Q2 to turn off the current source. At this point the collector voltage of Q4 sits at the circuit's input voltage. Q1 insures that the comparator will not self trigger if the input voltage increases during a ``hold'' interval. When a DC biased sine wave is applied to the circuit the sampled output is available at the circuit's output. The ramping action of the Q4 current source during the ``sample'' states is just visible in the output. [Schematic circuit source: National Semiconductor Notes].
In this circuit, the input-to-output wiring has similar to standard configuration, but its operating principle is different. Key advantages include simplicity, no hold step, essentially zero gain error and operation from a single 5V supply. The sample-hold command pulse is applied to Q3, which turns on, causing current source transistor Q4's collector to go to ground potential. Amplifier A1 follows Q4's collector voltage and provides the circuit's output. When the sample-hold command pulse falls, Q4's collector drives a constant current into the 0.01 mF capacitor.
When the capacitor ramp voltage equals the circuit's input voltage, comparator C1 switches, causing Q2 to turn off the current source. At this point the collector voltage of Q4 sits at the circuit's input voltage. Q1 insures that the comparator will not self trigger if the input voltage increases during a ``hold'' interval. When a DC biased sine wave is applied to the circuit the sampled output is available at the circuit's output. The ramping action of the Q4 current source during the ``sample'' states is just visible in the output. [Schematic circuit source: National Semiconductor Notes].
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